The following background information describes the MT48LC2M8S1, a 16 Meg synchronous dynamic random access memory (SDRAM) organized in a x8 configuration. The MT48LC2M8S1 is structured internally as a dual 1 Meg x8 SDRAM with synchronous interfacing and control logic. A dual 1 Meg x8 SDRAM has two banks, each bank comprises 8 memory arrays, and each memory array has 1 Meg (1,048,576) memory cells arranged in a matrix of electrical intersections of rows and columns. SDRAMs offer substantial advances in dynamic memory operating performance.
Two key advancements of the SDRAM are its ability to synchronously burst data at a high-speed data rate, via automatic column address generation, and to interleave between the internal banks hiding precharge time. The interleaving between two open banks increases the probability of "page-hits". The interleaving between open banks coupled with the high speed burst mode may, in many cases, provide a "seamless" flow of data.
When accessing the SDRAM, control circuitry is cycled in order to access one of the internal banks of memory. A typical synchronous design provides optimal memory performance in low voltage (typically 3.3V) memory systems. All input and output signals, with the exception of the clock enable (CKE) signal, are synchronized to the system's clock. The positive going edge of the system clock (CLK) provides the registering trigger which synchronizes the SDRAM.
The SDRAM has several programmable control operation features. The SDRAM must first be initialized and have its mode register set in order for the each programmable control operation feature to function according to a desired control operating option, also referred to as control operating mode. Once the mode register is set, the SDRAM may be accessed.
Each byte is uniquely accessed by registering the 11 row-address bits (A0-A10) via the Active command, followed by registering the 9 column-address bits (A0-A8) via a READ or WRITE command. Internal bank selection is controlled by a bank activate (BA) signal during both row address strobe (RAS) and column address strobe (CAS) registration which allows the bank to be accessed in order that a read/write operation may be performed to the bank. This bank selection is also called activation of the bank. The bank selected is referred to as an active or activated bank.
The SDRAM requires separate commands for accessing and precharging a row. Once a row is clocked into the SDRAM the bank becomes active and remains active. That is, the internally generated RAS* will remain active and the selected row will remain open until it is commanded to precharge via the precharge command. Throughout this specification letters which have the asterisk, such as RAS*, refer to the corresponding signal is RAS. Accidentally accessing another row in the same bank while the previous row is still active is not allowed and will result in deterioration of the memory's data in the bank being violated.
SDRAMs must be powered-up and initialized in a predefined manner. Operational procedures other than what is specified could produce unwanted and unrepeatable startup up modes. Once power, V.sub.CC and V.sub.OOQ, is simultaneously applied to core logic and DQ buffer power pins, respectively, the SDRAM requires a 100 micro second delay prior to any signals being toggled. It is recommended that all the inputs be held HIGH during this phase of powering-up.
It must be assumed that the SDRAM will power-up with its mode register in an unknown state. During initialization the signals on DQ pins are used as inputs to programming circuitries. There is a programming circuit for each programmable control operation feature and the programming circuitry programs the SDRAM for the desired control operating option in response to the mode register outputs. Thus, prior to performing any operational command, the SDRAM must have its mode register set.
The mode register is a persistent register. That is, once it is set, the data is latched to its outputs until it is reset or the device loses power.
FIG. 1 is a portion of SDRAM circuitry of the related art and comprises a mode register 3 programmed by providing an op-code, via the address inputs A0-A10, and ABA on address bus 5, in conjunction with a set mode register command generated in master control circuit 7. The mode register 3 is comprised of 11 D flip flop circuits which latch the op-code to the mode register output nodes on the positive going edge of the system clock when the mode register is enabled by the set mode register command. Programming circuits 8 select a control operating option for each programmable control operation feature of the SDRAM.
In FIG. 2 the control operating options of each programmable control operation feature are displayed in relation to the op-code 9 used to generate the desired control operating option. The op-code 9 is represented by bits MHz 0-M.sub.11. The programmable control operation features are burst length, burst type, and read latency and are shown in charts 10, 15, and 20, respectively. Other programmable control operation features are shown in chart 25. The programmable control operation features shown in charts 10, 15, and 20 are joint electron device engineering counsels (JEDEC) standards. The other programmable control operation features shown in chart 25 are vendor and application specific, except for "test mode entry" which is an agreed upon JEDEC standard.
The control operating option selected for the read latency feature shown in chart 20 is determined by the op-code M4 through M6; the sequential control operating option or the interleave operating option of the burst type feature, shown in chart 15, is determined by bit M3; and the operation option of the burst length feature, shown in chart 10 is determined by bits M.sub.0 through M.sub.2.
FIG. 3 is a block schematic of the related art showing the SDRAM MT48LC2M8S1, also described in the 1993 DRAM data book, published by Micron Technology herein incorporated by reference. The set mode register command is accomplished by registering chip select* (CS*), row access strobe* (RAS*), column address strobe* (CAS*) and write enable* (WE*) LOW during the idle state. The idle state occurs when all internal RAS signals are inactive, typically high. The set mode register command is generated in the master control circuit 19. The mode register command, the system clock, and the op-code on address input pins A0-A10 and BA are all received by the mode register 21.
Read latency is a programmable control operation feature defined by the op-code on address input pins A4-A6 in conjunction with the set mode register command. Address bits A4 through A6 define the number of clock cycles the data-out will be delayed or offset from its corresponding CAS registration during a READ cycle. Latencies of 1,2, or 3 clocks are available as shown in chart 20 of FIG. 2. The read latency guarantees on which clock the data will be available, regardless of clock rate (TCK).
Burst type is a programmable control operation feature defined by the op-code on address input pin A3 in conjunction with the set mode register command. Address input bit A3 defines which burst type option is invoked as shown in chart 15 block of FIG. 2.
The two types of burst type options available for selection are sequential and interleave. Both sequential and interleave sequencing support bursts of 2, 4, and 8 cycles. Additionally, sequential sequencing supports the full-page length option.
The burst length is a programmable control operation feature defined by the op-code on address input pins A0-A2 in conjunction with the set mode register command. Address bits 2 through 0 define the burst length and are shown in chart 10 of FIG. 2.
The burst length provides for a continuous flow of data starting at the specified memory location during a READ or a WRITE access. Burst length options of 2, 4, 8 or full-page cycles may be programmed.
Once the mode register of a typical SDRAM is programmed it takes many clock cycles to reprogram the mode register because all of the memory banks need to be in the inactive state. For example, if the mode register of the MT48LC2M8S1 was programmed to have a sequential burst type during initialization it would take 11 clock cycles to reprogram the mode register to an interleave burst type, see FIG. 4 which is a timing diagram depicting the many clock cycles necessary to reprogram the MT48LC2M8S1 of the related art. Similar problems are encountered when reprogramming the other control operation features of the mode register.
The JEDEC-defined standard requires the type of sequencing to be programmed to the mode register. Each time the type of sequencing needs to be changed, the program register must be reprogrammed. Several cycles of overhead are required each time the program register must be reprogrammed. Thus, changing the type of sequencing during operation results in a significant time penalty. Consequently there exists a need to minimize the time required to reprogram the mode register, thereby increasing the processing speed.